View IS49NLS18160_5990323.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 1 288 m b (x9, x18) separate i/o r ldram ? 2 memory features ? 533mhz ddr operation (1.067 gb/s/pin data rate) ? 38.4 gb/s peak bandwidth (x 18 separate i/o at 533 mhz clock frequency) ? reduced cycle time (15ns at 533mhz) ? 32 ms refresh (8 k refresh for each bank; 64k refresh command must be issued in total each 32 ms) ? 8 internal banks ? non - multiplexed addresses (address multiplexing option available) ? sram - type interface ? programmable read latency (rl), row cycle time, and burst sequence length ? balanced read and write lat encies in order to optimize data bus utilization ? data mask signals (dm) to mask signal of write data; dm is sampled on both edges of dk. ? differential input clocks (ck, ck#) ? differential input data clocks (dkx, dkx#) ? on - die dll generates ck edge - aligned dat a and output data clock signals ? data valid signal (qvld) ? hstl i/o (1.5v or 1.8v nominal) ? 25- 60 matched impedance outputs ? 2.5v v ext , 1.8v v dd , 1.5v or 1.8v v ddq i/o ? on - die termination (odt) r tt ? ieee 1149.1 compliant jtag boundary scan ? operating temperature: commercial (t c = 0 to + 95c; t a = 0c to +70c), industrial ( t c = - 40c to +95c ; t a = - 40 c to +85c) options ? package: ? 144- ball f bga (leaded) ? 144- ball f bga (lead - free) ? configuration: ? 32 mx9 ? 16 mx18 ? clock cycle timing: speed grade - 18 - 25e - 25 - 33 unit t rc 15 15 20 20 ns t ck 1.875 2.5 2.5 3.3 ns copyright ? 2012 integrated silicon solution, i nc. all rights reserved. issi reserves the right to make changes to this specification and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described he rein. c ustomers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for product s. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. pr oducts are not authorized for use in such applications unl ess integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequate ly protected under the circumstances rldram ? is a registered trademark of mi cron technology, inc. advanced information september 2012
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 2 1 package ballout and description 1.1 288mb (32mx9) separate i/o bga ball - out (top view) 1 2 3 4 5 6 7 8 9 10 11 12 a vref vss vext vss vss vext tms tck b vdd dnu 3 dnu 3 vssq vssq q0 d0 vdd c vtt dnu 3 dnu 3 vddq vddq q1 d1 vtt d a22 1 dnu 3 dnu 3 vssq vssq qk0# qk0 vss e a21 1 dnu 3 dnu 3 vddq vddq q2 d2 a20 f a5 dnu 3 dnu 3 vssq vssq q3 d3 qvld g a8 a6 a7 vdd vdd a2 a1 a0 h ba2 a9 vss vss vss vss a4 a3 j nf 2 nf 2 vdd vdd vdd vdd ba0 ck k dk dk# vdd vdd vdd vdd ba1 ck# l ref# cs# vss vss vss vss a14 a13 m we# a16 a17 vdd vdd a12 a11 a10 n a18 dnu 3 dnu 3 vssq vssq q4 d4 a19 p a15 dnu 3 dnu 3 vddq vddq q5 d5 dm r vss dnu 3 dnu 3 vssq vssq q6 d6 vss t vtt dnu 3 dnu 3 vddq vddq q7 d7 vtt u vdd dnu 3 dnu 3 vssq vssq q8 d8 vdd v vref zq vext vss vss vext tdo tdi symbol description ball count vdd supply voltage 16 vss ground 16 vddq dq power supply 8 vssq dq ground 12 vext supply voltage 4 vref reference voltage 2 vtt termination voltage 4 a* address - a0-22 23 ba* banks - ba0-2 3 d* input data 9 q* output data 9 dk* input data clock(differential inputs) 2 qk* output data clocks(outputs) 2 ck* input clocks (ck, ck#) 2 dm input data mask 1 cs#,we#,ref# command control pins 3 zq external impedance (25C60) 1 qvld data valid 1 dnu,nf do not use, no function 22 t* jtag - tck,tms,tdo,tdi 4 total 144 notes: 1) reserved for future use. this may optionally be connected to gnd. 2) reserved for future use. this signal is internally connected and has parasitic characteristics of an address input signal. this may optionally be connected to gnd. 3) no function. this signal is internally connected and has parasitic characteristics of a clock input signal. this may optionally be connected to gnd. 4) do not use. this signal is internally connected and has parasitic characteristics of a i/o. this may optionally be connected to gnd. note that if odt is enabled, these pins will be connected to vtt. notes: 1) reserved for future use. this may optionally be connected to gnd. 2) reserved for future use. this signal is internally connected and has parasitic characteristics of an address input signal. this may optionally be connected to gnd. notes: 1. reserved for future use. this may optionally be connected to gnd. 2. no function. this signal is internally connected and has parasitic characteristics of a clock input signal. this may optionally be connected to gnd. 3. do not use. this signal is internally connected and has parasitic characteristics of a i/o. this may optionally be connected to gnd. note that if odt is enabled, these pins are high - z.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 3 1.2 288 mb ( 16 mx18) separate i/o bga ball - out (top view) 1 2 3 4 5 6 7 8 9 10 11 12 a vref vss vext vss vss vext tms tck b vdd d4 q4 vssq vssq q0 d0 vdd c vtt d5 q5 vddq vddq q1 d1 vtt d a22 1 d6 q6 vssq vssq qk0# qk0 vss e a21 2 d7 q7 vddq vddq q2 d2 a20 2 f a5 d8 q8 vssq vssq q3 d3 qvld g a8 a6 a7 vdd vdd a2 a1 a0 h ba2 a9 vss vss vss vss a4 a3 j nf 3 nf 3 vdd vdd vdd vdd ba0 ck k dk dk# vdd vdd vdd vdd ba1 ck# l ref# cs# vss vss vss vss a14 a13 m we# a16 a17 vdd vdd a12 a11 a10 n a18 d14 q14 vssq vssq q9 d9 a19 p a15 d15 q15 vddq vddq q10 d10 dm r vss qk1 qk1# vssq vssq q11 d11 vss t vtt d16 q16 vddq vddq q12 d12 vtt u vdd d17 q17 vssq vssq q13 d13 vdd v vref zq vext vss vss vext tdo tdi symbol description ball count vdd supply voltage 16 vss ground 16 vddq dq power supply 8 vssq dq ground 12 vext supply voltage 4 vref reference voltage 2 vtt termination voltage 4 a* address - a0-22 23 ba* banks - ba0-2 3 d* input data 18 q* output data 18 dk* input data clock(differential inputs) 2 qk* output data clocks(outputs) 4 ck* input clocks (ck, ck#) 2 dm input data mask 1 cs#,we#,ref# command control pins 3 zq external impedance (25C60) 1 qvld data valid 1 nf do not use, no function 2 t* jtag - tck,tms,tdo,tdi 4 total 144 notes: 1) reserved for future use. this may optionally be connected to gnd. 2) reserved for future use. this signal is internally connected and has parasitic characteristics of an address input signal. this may optionally be connected to gnd. 3) no function. this signal is internally connected and has parasitic characteristics of a clock input signal. this may optionally be connected to gnd. 4) do not use. this signal is internally connected and has parasitic characteristics of a i/o. this may optionally be connected to gnd. note that if odt is enabled, these pins will be connected to vtt. notes: 1) reserved for future use. this may optionally be connected to gnd. 2) reserved for future use. this signal is internally connected and has parasitic characteristics of an address input signal. this may optionally be connected to gnd. 3) no function. this signal is internally connected and has parasitic characteristics of a clock input signal. this may optionally be connected to gnd. 4) do not use. this signal is internally connected and has parasitic characteristics of a i/o. this may optionally be connected to gnd. note that if odt is enabled, these pins will be connected to vtt. notes: 1. reserved for future use. this may optionally be connected to gnd. 2. reserved for future use. this signal is internally connected and has parasitic characteristics of an address input signal. this may optionally be connected to gnd. 3. no function. this signal is internally connected and has parasitic characteristics of a clock input signal. this may optionally be connected to gnd.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 4 1.3 ball descriptions symbol type description a* input address inputs: defines the row and column addresses for read and write operations. during a mode register set, the address inputs define the register settings. they are sampled at t he rising edge of ck. ba* input bank address inputs: selects to which internal bank a command is being applied to. ck, ck# input input clock: ck and ck# are differential input clocks. addresses and commands are latched on the rising edge of ck. ck# is id eally 180 degrees out of phase with ck. cs# input chip select: cs# enables the command decoder when low and disables it when high. when the command decoder is disabled, new commands are ignored, but internal operations continue. d* input data input: the d signals form the input data bus. during write commands, the data is sampled at both edges of dk. dk, dk# input input data clock: dk* and dk*# are the differential input data clocks. all input data is referenced to both edges of dk*. dk*# is ideally 180 degrees out of phase with dk*. for both the x9 and x18 devices, all d signals are referenced to dk and dk#. dk and dk# pins must always be supplied to the device. dm input input data mask: the dm signal is the input mask signal for write data. input data is masked when dm is sampled high. dm is sampled on both edges of dk. tie signal to ground if not used. tck input ieee 1149.1 clock input: this ball must be tied to v ss if the jtag function is not used. tms,tdi input ieee 1149.1 test inputs: these balls may be left as no connects if the jtag function is not used. we#, ref# input command inputs: sampled at the positive edge of ck, we# and ref# define (together with cs#) the command to be executed. v ref input input reference voltage: nominally v ddq /2. pro vides a reference voltage for the input buffers. zq i/o external impedance (25 C 60): this signal is used to tune the device outputs to the system data bus impedance . q output impedance is set to 0.2 rq, where rq is a resistor from this signal to ground. connecting zq to gnd invokes the minimum impedance mode. q* output data input: the q signals form the output data bus. during read commands, the data is referenced to both edges of qk* qk*, qk*# output output data clocks: qk* and qk*# are opposite polarity, output data clocks. they are free running, and durin g reads, are edge - aligned with data output from the memory . qk*# is ideally 180 degrees out of phase with qk*. for the x18 device, qk0 and qk0# are aligned with q0 - q8, while qk1 and qk1# are aligned with q9 - q17. for the x9 device, all q signals are aligned with qk0 and qk0#. qvld output data valid: the qvld pin indicates valid output data. qvld is edge - aligned with qk* and qk*# . tdo output ieee 1149.1 test output: jtag output. this ball may be left as no connect if the jtag function is not used. v dd supp ly power supply: nominally, 1.8v. v ddq supply dq power supply: nominally, 1.5v or 1.8v. isolated on the device for improved noise immunity. v ext supply power supply: nominally, 2.5v v ss supply ground . v ssq supply dq ground: isolated on the device for i mproved noise immunity. v tt supply power supply: isolated termination supply. nominally, v ddq /2. dnu - do not use: these balls may be connected to ground. note that if odt is enabled, these pins are high - z. nf - no function: these balls can be connected to ground
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 5 2 electrical specifications 2.1 absolute maximum ratings item min max units i/o voltage 0.3 v ddq + 0.3 v voltage on v ext supply relative to v ss 0.3 2.8 v voltage on v dd supply relative to v ss 0.3 2.1 v voltage on v ddq supply relative to v ss 0.3 2.1 v note : stress greater than those listed in this table may cause permanent damage to the device. this is a stress rating only and f unctional operation of the device at these or any other conditions above those indicated in the operational secti ons of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2.2 dc electrical characteristics and operating conditions description conditions symbol min max units notes supply volta ge v ext 2.38 2.63 v supply voltage v dd 1.7 1.9 v 2 isolated output buffer supply v ddq 1.4 v dd v 2,3 reference voltage v ref 0.49 x v ddq 0.51 x v ddq v 4,5,6 termination voltage v tt 0.95 x v ref 1.05 x v ref v 7,8 input high voltage v ih v ref + 0.1 v ddq + 0.3 v 2 input low voltage v il v ssq ? 0.3 v ref ? 0.1 v 2 output high current v oh = v ddq /2 i oh (v ddq /2)/ (v ddq /2)/ a 9, 10, 11 (1.15 x rq/5) (0.85 x rq/5) output low current v ol = v ddq /2 i ol (v ddq /2)/ (v ddq /2)/ a 9, 10, 11 (1.15 x rq/5) (0.85 x rq/5) clock input leakage current 0v v in v dd i lc ? 5 5 a input leakage current 0v v in v dd i li ? 5 5 a output leakage current 0v v in v ddq i lo ? 5 5 a reference voltage current i ref ? 5 5 a notes : 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih (ac) v dd + 0.7v for t t ck /2. undershoot: v il (ac) C 0.5v for t t ck /2. during normal operation, v ddq must not exceed v dd . control input signals may not have pulse widths less than t ck /2 or operate at frequencies exceeding t ck (max). 3. v ddq can be set to a nomina l 1.5v 0.1v or 1.8v 0.1v supply. 4. typically the value of v ref is expected to be 0.5 x v ddq of the transmitting device. v ref is expected to track variations in v ddq . 5. peak - to - peak ac noise on v ref must not exceed 2 percent v ref (dc). 6. v ref is expected to equal v ddq /2 of the transmitting device and to track variations in the dc level of the same. peak - to - peak noise (non - common mode) on v ref may not exceed 2 percent of the dc value. thus, from v ddq /2, v ref is allowed 2 percent v ddq /2 for dc error and an ad ditional 2 percent v ddq /2 for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 7. v tt is expected to be set equal to v ref and must track variations in the dc level of v re f . 8. on - die termination may be selected using mode register a9 (for non - multiplexed address mode) or ax9 (for multiplexed address mode). a resistance r tt from each data input signal to the nearest v tt can be enabled. r tt = 125 C 185 at 95c t c . 9. i oh and i ol are defined as absolute values and are measured at v ddq /2. i oh flows from the device, i ol flows into the device. 10. if mrs bit a8 or ax8 is 0, use rq = 250 in the equation in lieu of presence of an external impedance matc hed resistor. 2.3 capacitance (t a = 25 c, f = 1mhz) parameter symbol test conditions min max units address / control input capacitance c in v in =0v 1.5 2.5 pf i/o, output, o ther capacitance (d, q, dm, qk, qvld) c io v io =0v 3.5 5 pf clock input capacitanc e c clk v clk =0v 2 3 pf jtag pins c j v j =0v 2 5 pf note. these parameters are not 100% tested and c apacitance is not tested on zq pin.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 6 2.4 operating conditions and maximum limits description condition symbol - 18 - 25e - 25 - 33 units standby current t ck = id le; all banks idle; no inputs toggling isb1(v dd ) x9/x18 55 53 48 48 ma isb1(v ext ) 5 5 5 5 ma active standby current cs# =1; no commands; bank address incremented and half address/data change once every 4 clock cycles isb2(v dd ) x9/x18 365 293 288 233 ma isb2(v ext ) 5 5 5 5 ma operational current bl=2; sequential bank access; bank transitions once every t rc ; half address transitions once every t rc ; read followed by write sequence; continuous data during write commands idd1(v dd ) x9/x18 465 380 348 305 m a idd1(v ext ) 15 15 15 13 ma bl = 4; sequential bank access; bank transitions once every t rc ; half address transitions once every t rc ; read followed by write sequence; continuous data during write commands idd2(v dd ) x9/x18 475 400 362 319 ma idd2(v e xt ) 15 15 15 13 ma bl = 8; sequential bank access; bank transitions once every t rc ; half address transitions once every t rc ; read followed by write sequence; continuous data during write commands idd3 (v dd ) x9/x18 505 430 408 368 ma idd3(v ext ) 20 20 2 0 18 ma burst refresh current eight - bank cyclic refresh; continuous address/data; command bus remains in refresh for all eight banks iref1(v dd ) x9/x18 995 790 785 615 ma iref1(v ext ) 80 80 80 70 ma distributed refresh current single - bank refresh; seque ntial bank access; half address transitions once every t rc , continuous data iref2(v dd ) x9/x18 425 330 325 267 ma iref2(v ext ) 20 20 20 18 ma operating burst write current bl=2; cyclic bank access; half of address bits change every clock cycle; continuou s data; measurement is taken during continuous write idd2w(v dd ) x9/x18 1335 980 970 819 ma idd2w(v ext ) 50 50 50 40 ma bl=4; cyclic bank access; half of address bits change every 2 clock cycles; continuous data; measurement is taken during continuous w rite idd4w(v dd ) x9/x18 985 785 779 609 ma idd4w(v ext ) 30 30 30 25 ma bl=8; cyclic bank access; half of address bits change every 4 clock cycles; continuous data; measurement is taken during continuous write idd8w(v dd ) x9/x18 770 675 668 525 ma idd8 w(v ext ) 30 30 30 25 ma operating burst read current bl=2; cyclic bank access; half of address bits change every clock cycle; measurement is taken during continuous read idd2r(v dd ) x9/x18 1225 865 860 735 ma idd2r(v ext ) 50 50 50 40 ma bl=4; cyclic ban k access; half of address bits change every clock cycle; measurement is taken during continuous read idd4r(v dd ) x9/x18 860 685 680 525 ma idd4r(v ext ) 30 30 30 25 ma bl=8; cyclic bank access; half of address bits change every clock cycle; measurement i s taken during continuous read idd8r(v dd ) x9/x18 655 575 570 450 ma idd8r(v ext ) 30 30 30 25 ma
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 7 notes : 1) idd specifications are tested after the device is properly initialized. +0c t c +95c; +1.7v v dd +1.9v, +2.38v v ext +2.63v, +1.4v v ddq v dd , v ref = v ddq /2. 2) t ck = t dk = min, t rc = min. 3) definitions for idd conditions: a. low is defined as v in v il (ac) max. b. high is defined as v in v ih (ac) min. c. stable is defined as inputs remaining at a high or low level. d. floating is defined as inputs at v re f = v ddq /2. e. continuous data is defined as half the d or q signals changing between high and low every half clock cycle (twice per clock). f. continuous address is defined as half the address signals changing between high and low every clock cycle (once per cl ock). g. sequential bank access is defined as the bank address incrementing by one every t rc . h. cyclic bank access is defined as the bank address incrementing by one for each command access. for bl = 2 this is every clock , for bl = 4 this is every other clock, and for bl = 8 this is every fourth clock. 4) cs# is high unless a read, write, aref, or mrs command is registered. cs# never transitions more than once per clock cycle. 5) idd parameters are specified with odt disabled. 6) tests for ac timing, idd, and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operations are tested for the full voltage range specified. 7) idd tests may use a v il - to - v ih swing of up to 1.5v in the test envi ronment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#). parameter specifications are tested for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the dev ice is 2 v/ns in the range between v il (ac) and v ih (ac). 2.5 recommended ac operating conditions ( +0c t c +95c; +1.7v v dd +1.9v, unless otherwise noted. ) parameter symbol min max units input high voltage v ih (ac) v ref + 0.2 - v input low voltage v il (ac) - v ref C 0.2 v note s : 1. overshoot: v ih (ac) v ddq + 0.7v for t t ck /2 2. undershoot: v il (a c) C 0.5v for t t ck /2 3. control input signals may not have pulse widths less than t ckh (min) or operate at cycle rates less than t ck (min.). 2.6 temperature and thermal impedance temperature limits parameter symbol min max units reliability junction tempe rature 1 t j 0 110 c operating junction temperature 2 t j 0 100 c operating case temperature 3 t c 0 95 c note s: 1. temperatures greater than 110c may cause permanent damage to the device. this is a stress rating only and functional operation of the devic e at or above this is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability of the part. 2. junction temperature depends upon cycle time, loading, ambient temperature, and airflow. 3. max operating case temperatu re; t c is measured in the center of the package. device functionality is not guaranteed if the device exceeds maximum t c during operation. thermal resistance package substrate theta - ja (airflow = 0m/s) theta - ja (airflow = 1m/s) theta - ja (airflow = 2m /s) theta - jc unit 144- ball fbga 4 - layer 20.6 19.1 17.2 2.4 c/w
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 8 2.7 ac electrical characteristics (1, 2, 3, 4) description symbol - 18 (1.875ns @trc=15ns) - 25e (2.5ns @t rc =15ns) - 25 (2.5ns @trc=20ns) - 33 (3.3ns @trc=20ns) units min max min m ax min max min max input clock cycle time t ck 1.875 2.7 2.5 5.7 2.5 5.7 3.3 5.7 ns input data clock cycle time t dk tck C tck C tck C tck C ns clock jitter: period (5, 6) t jitper C 100 100 C 150 150 C 150 150 C 200 200 ps clock jitter: cycle - to - cycle t jit cc C 200 C 300 C 300 C 400 ps clock high time t ckh / t dkh 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low time t ckl / t dkl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock to input data clock t ckdk C 0.3 0.3 C 0.45 0.5 C 0.45 0.5 C 0.45 1.2 ns mode regi ster set cycle time to any command t mrsc 6 C 6 C 6 C 6 C t ck address/command and input setup time t as /t cs 0.3 C 0.4 C 0.4 C 0.5 C ns data - in and data mask to dk setup time t ds 0.17 C 0.25 C 0.25 C 0.3 C ns address/command and input hold time t ah /t ch 0.3 C 0.4 C 0.4 C 0.5 C ns data - in and data mask to dk hold time t dh 0.17 C 0.25 C 0.25 C 0.3 C ns output data clock high time t qkh 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ckh output data clock low time t qkl 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ck l half - clock period t qhp min(t qkh , t qkl ) C min(t qkh , t qkl ) C min(t qkh , t qkl ) C min(t qkh , t qkl ) C qk edge to clock edge skew t ckqk C 0.2 0.2 C 0.25 0.25 C 0.25 0.25 C 0.3 0.3 ns qk edge to output data edge (7) t qkq0 , C 0.12 0.12 C 0.2 0.2 C 0.2 0.2 C 0.25 0.25 ns t qkq1 qk edge to any output data edge (8) t qkq C 0.22 0.22 C 0.3 0.3 C 0.3 0.3 C 0.35 0.35 ns qk edge to qvld t qkvld C 0.22 0.22 C 0.3 0.3 C 0.3 0.3 C 0.35 0.35 ns data valid window t dvw t qhp - C t qhp - C t qhp - C t qhp - C (t qkqx (t qkqx (t qkqx (t qkqx [max] + [max] + [max] + [max] + |t qkqx |t qkqx |t qkqx |t qkqx [min]|) [min]|) [min]|) [min]|) average periodic refresh interval (9) t refi C 0.49 C 0.49 C 0.49 C 0.49 s
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 9 notes : 1. all timing parameters are measured relative to the crossing point of ck/ck#, dk/dk# and to the crossing point with v ref of the command, address, and data signals. 2. outputs measured with equivalent load: 10 pf 50 test point q v tt 3. tests for ac timing, idd, and electrical ac and dc characteristic s may be conducted at nominal reference/supply voltage levels, but the related specifications and device operations are tested for the full voltage range specified. 4. ac timing may use a v il - to - v ih swing of up to 1.5v in the test environment, but input timin g is still referenced to v ref (or to the crossing point for ck/ck#), and parameter specifications are tested for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 2 v/ns in the range between v il (ac) and v ih (ac). 5. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 6. frequency drift is not allowed. 7. for a x18 device, q0 C q8 is referenced to t qkq0 and q9 C q17 is referenced to t qkq1 . for a x9 device, q0 C q8 is referenced to t qkq0 . 8. t qkq takes into account the skew between any qk x and any q. 9. to improve efficiency, eight aref commands (one for each b ank) can be posted to the memory on consecutive cycles at periodic intervals of 3.90 s. 2.8 clock i nput conditions differential input clock operating conditions parameter symbol min max units notes clock input voltage level v in (dc) - 0.3 v ddq +0.3 v clock input differential voltage level v id (dc) 0.2 v ddq +0.6 v 8 clock input differential voltage level v id (ac) 0 .4 v ddq +0.6 v 8 clock input crossing point voltage level v ix (ac) v ddq /2 - 0. 1 5 v ddq /2+0. 1 5 v 9 clock input e xample ck# v ddq /2 ck v ddq /2+0.15v, v ix (ac) max v ddq /2-0.15v, v ix (ac) min (10) v id (dc) (11) v id (ac) (12) notes : 1. dkx and dkx# have the same requirements as ck and ck#. 2. all voltages referenced to v ss . 3. tests for ac timing, idd and electrical ac and dc characteristics may be conducted at normal reference/supply voltage levels; but the related specifications and device operations are tested for the full voltage range specified. 4. ac timing and idd tests may use a v il to v ih swing of up to 1.5 v in the test environment, but input timing is still referenced to v ref (or the crossing point for ck/ck#), and parameters specifications are tested for the specified ac input levels under normal use conditions. the minimum sle w rate for the input signals used to test the device is 2v/ns in the range between v il (ac) and v ih (ac).
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 10 5. the ac and dc input level specifications are as defined in the hstl standard (i.e. the receiver will effectively switch as a result of the signal crossi ng the ac input level, and will remain in that state as long as the signal does not ring back above[below] the dc input low[high] level). 6. the ck/ck# input reference level (for timing referenced to ck/ck#) is the point at which ck and ck# cross. the input r eference level for signal other than ck/ck# is v ref . 7. ck and ck# input slew rate must be 2v/ns ( 4v/ns if measured differentially). 8. v id is the magnitude of the difference between the input level on ck and input level on ck#. 9. the value of v ix is expected to equal v ddq /2 of the transmitting device and must track variations in the dc level of the same. 10. ck and ck# must cross within the region. 11. ck and ck# must meet at least v id (dc) (min.) when static and centered around v ddq /2. 12. minimum peak - to - peak swing.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 11 3 functional descriptions 3.1 power - up and initialization (1) the r ldram ? 2 memory must be powered - up and initialized using the specific steps listed below: 1. apply power by ramping up supply voltages v ext , v dd , v ddq , v ref , and v tt . apply v dd and v ext before o r at the same time as v ddq (2) . power - up sequence begins when both v dd and v ext approach their nominal levels. afterwards, apply v ddq before or at the same time as v ref and v tt . once the supply voltages are stable, clock inputs ck/ck# and dk/dk# can be app lied. register nop commands to the control pins to avoid issuing unwanted commands to the device. 2. keep applying stable conditions for a minimum of 200 s. 3. register at least three consecutive mrs commands consisting of two or more dummy mrs commands and one valid mrs command. timing parameter t mrsc is not required to be met during these consecutive mrs commands but asserting a low logic to the address signals is recommended. 4. t mrsc timing delay after the valid mrs command, auto refresh commands to all 8 bank s and 1,024 nop commands must be issued prior to normal operation. the auto refresh commands to the 8 banks can be issued in any order with respect to the 1,024 nop commands. please note that the t rc timing parameter must be met between an auto refresh com mand and a valid command in the same bank. 5. the device is now ready for normal operation. notes : 1. operational procedure other than the one listed above may result in undefined operations and may permanently damage the devic e. 2. v ddq can be applied before v dd but will result in all d and q data pin s , dm, and other pins with an output driver to go logic high (instead of tri - state) and will remain high until the v dd is the same level as v ddq . this method is not recommended to avoid bus conflicts during the power - up. 3.2 power - up and initialization flowchart v dd and vext ramp up (1) v ddq ramp up (1) v ref and v tt ramp up (1) apply stable ck/ck# and dk/dk# wait 200 s minimum issue dummy 1 st mrs command (2) issue dummy 2 nd mrs command (2) issue valid 3 rd mrs command (2) assert nop for t mrs issue aref commands to all 8 banks (3) issue 1,024 nop commands (3) rldram is now ready for normal operation notes : 1. the supply voltages can be ramped up simultaneously. 2. the dummy and valid mrs commands must be issued in consecutive clock cycles. at least two dummy mrs commands are requi red. it is recommended to assert a low logic on the address signals during the dummy mrs commands. 3. the auto refresh commands can be issued in any order with respect to the 1,024 nop commands. however, timing parameter t rc must be met before issuing any val id command in a bank after an aref command to the same bank has been issued.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 12 3.3 power - up an d initialization timing diagram non - m ultiplexed address mode ck ck # command v ext , v dd , v ddq , v ref , v tt nop nop ~~ 200us(min) mrs 1, 2 mrs 1, 2 mrs 2 nop ~~ aref- ba0 ~~ aref- ba7 refresh all 8 banks dont care ~~ t ckh t ckl t ck t mrsc any 5 1024 nops notes : 1. it is recommended that the address input signals be driven low during the dummy mrs commands. 2. a10 C a17 must be low. 3. dll must be reset if t ck or v dd are changed. 4. ck and ck# must be separated at all times to prevent invalid commands from being issued. 5. the auto refresh commands can be issued in any order with respect to the 1,0 24 nop commands. however, timing parameter t rc must be met before issuing any valid command in a bank after an aref command to the same bank has been issued. multiplexed address mode ck ck # command v ext , v dd , v ddq , v ref , v tt nop nop 200us(min) mrs mrs mrs ~ ~ nop ~~ aref refresh all 8 banks aref dont care ~~ t ckh t ckl t ck t mrsc address a 1,2 a 1, 2 a 2, 3 ay bank0 bank7 ~~ mrs ax 2,4 t mrsc ~~ any any 1024 nops 6 notes : 1. it is recommended that the address input signals be driven low during the dummy mrs commands. 2. a10 C a1 8 must be low.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 13 3. set address a5 high. this enables the part to enter mu ltiplexed address mode when in n on - multiplexed mode operation. multiplexed address mode can also be entered at some later time by issuing an mrs command with a5 high. once address bit a5 is set high, t mrsc must be satisfied before the two cycle multiplexed mode mrs command is issued. 4. address a5 must be set high. this and the following step set the desir ed mode register once t he memory is in multiplexed address mode. 5. ck and ck# must be separated at all times to prevent invalid commands from being issued. 6. the auto refresh commands can be issued in any order with respect to the 1,024 nop commands. however, timing parameter t rc mu st be met before issuing any valid command (any) in a bank after an aref command to the same bank has been issued. 3.4 mode register setting and features . code cs# we# ref# ck ck # add ax ay t mrsc dont care mrs - multiplexed mode mrs - non -multiplexed mode t mrsc any valid valid any valid valid note: the mrs command can only be issued when all banks are id l e and no b ursts are in progress.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 14 the mode register set command stores the data for controlling the vario us operating modes of the memory using address inputs a0 - a17 as mode registers. during the mrs command, the cycle time and the read/write latency of the memory c an be selected from different configurations. the mrs command also programs the memory to operate in either multiplexed address mode or non - multiplexed address mode. in addition, several features can be enabled using the mrs command. these are the dll, dri ve impedance matching, an d on - die termination (odt). t mrsc must be met before any command can be issued . t mrsc is measured like the picture above in both multiplexed and n on - m ultiplexed mode. mode register diagram (non - multiplexed address mode) a9 0 1 a8 0 1 a7 0 1 a5 0 1 a4 a3 0 0 0 1 1 0 1 1 a2 a1 a0 trc(tck) trl(tck) twl(tck) 0 0 0 4 4 5 0 0 1 4 4 5 0 1 0 6 6 7 0 1 1 8 8 9 1 0 0 3 3 4 1 0 1 5 5 6 1 1 0 n/a n/a n/a 1 1 1 n/a n/a n/a a10-17 m10-17 0 1 on address field mode register on-die termination off (default) a8 m8 im external(zq) a9 m9 odt drive impedance internal 50 5 (default) a6 m6 na 2 dll enable a7 m7 dll dll reset dll reset 4 (default) m3 burst length(bl) 2 a5 m5 am address mux non-multiplexed (default) a1 m1 reserved a0 m0 a4 m4 bl multiplexed a3 read/write latency and cycle time configuration 6,7 valid frequency range (mhz) configuration 1 3 (default) 266-175 a2 m2 config 4 8 3 533-175 4 3,8 200-175 1 3 266-175 2 400-175 reserved n/a 5 333-175 reserved n/a notes : 1. a10 - a17 must be set to zero; a18 - an are "don't cares." 2. a6 not used in mrs. 3. bl = 8 is not available. 4. dll reset turns the dll off. 5. 30 % temperature variation. 6. t rc < 20ns in any configuration is only available with - 25e and - 18 speed grades. 7. minimum operating frequency for - 18 is 370mhz. 8. the minimum t rc is typically 3 cycles, except in the case of a write followed by a read to the same bank. in this instance the minimum t rc is 4 cycles.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 15 mode register diagram (multiplexed address mode ) a9 0 1 a8 0 1 a7 0 1 a5 0 1 a4 a3 0 0 0 1 1 0 1 1 ay4 ay3 ax0 trc(tck) trl(tck) twl(tck) 0 0 0 4 5 6 0 0 1 4 5 6 0 1 0 6 7 8 0 1 1 8 9 10 1 0 0 3 4 5 1 0 1 5 6 7 1 1 0 n/a n/a n/a 1 1 1 n/a n/a n/a on-die termination off (default) m10-18 0 1 on ax ay mode register im a9 m9 odt m8 drive impedance internal 50 6 (default) a10-18 a10-18 m6 na 5 external(zq) a9 m7 dll dll reset dll reset 4 (default) a8 bl dll enable address mux non-multiplexed (default) a5 m5 am a8 m0 multiplexed a3 m3 burst length(bl) 2 (default) a4 m4 a3 m1 reserved a4 m2 config a0 read/write latency and cycle time configuration 8,9 valid frequency range (mhz) configuration 1 2 (default) 266-175 4 8 3 533-175 4 2,10 200-175 1 2 266-175 2 400-175 reserved n/a 5 333-175 reserved n/a notes : 1. a10 - a18 must be set to zero; a1 9- an are "don't cares." 2. bl = 8 is not available. 3. 30 % temperature variation. 4. dll reset turns the dll off. 5. ay = 8 is not used in mrs. 6. ba0 - ba2 are "don't care ." 7. addresses a0, a3, a4, a5, a8, and a9 must be set as shown in order to activate the mode register in the multiplexed address mode. 8. t rc < 20ns in any configuration is only available with - 25e and - 18 speed grades. 9. minimum operating frequency for - 18 is 370mhz. 10. the minimum trc is typical ly 3 cycles, except in the case of a write followed by a read to the same bank. in this instance the minimum t rc is 4 cycles.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 16 3.5 mode register bit description configuration the cycle time and read/write latency can be configured from the different optio ns shown in the mode register diagram. in order to maximize data bus utilization, the write latency is equal to read latency plus one. the read and write latencies are increase d by one clock cycle during multiplexed address mode compared to non - multiplexed mode. burst length the burst length of the r ead and write accesses to memory can be selected from three different options: 2, 4, and 8. changes in the burst length affect the width of the address bus and is shown in the burst length and address width tab le . the data written during a prior burst length setting is not guaranteed to be accurate when the burst length of the device is changed. burst length and address width table burst length 288 mb address bus x9 x18 2 a0 - a2 0 a0 - a 19 4 a0 - a 19 a0 - a1 8 8 a0 - a 18 a0 - a1 7 dll reset the default setting for this option is low, whereby the dll is disabled. once the mode register for this feature is set high, 1024 cycles (5s at 200 mhz) are needed before a read command can be issued. this time allows the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t ckqk parameter. a reset of the dll is necessary if t ck or v dd is changed after the dll has already been enabled. to reset the d ll, an mrs command must be issued where the dll reset mode register is set low. after waiting t mrsc , a subsequent mrs command should be issued whereby the dll reset mode register is set high. 1024 clock cycles are then needed before a read command is issue d. drive impedance matching the r ldram ? 2 memory is equipped with programmable impedance output buffers. the purpose of the programmable impedance output buffers is to allow the user to match the driver impedance to the system. to adjust the impedance, a n external precision resistor (rq) is connected between the zq ball and v ss . the value of the resistor must be five times the desired impedance. for examp le, a 300 resistor is required for an output impedance of 60. the range of rq is 125 C 300, which guarantees output impedance in the range of 25 C 60 (within 15 percent). output impedance updates may be required because over time variations may occur in su pply voltage and temperature. when the external drive impedance is enabled in the mrs, the device will periodically sample the value of rq. an impedance update is transparent to the system and does not affect device operation. all data sheet timing and cur rent specifications are met during an update. when the drive impedance mode register is set low du ring the mrs command, the memory provides an internal impedance at the output buffer of 50 (30% with temperature variation). this impedance is also periodically sampled and adjusted to compensate for variation in supply voltage and temperature. address multiplexing although the r ldram ? 2 memory is capabl e of accepting all the addresses in a sing le rising clock edge, this memory can be programmed to operate in multiplexed address mode, which is very similar to a traditional dram. in multiplexed address mode, the a ddress can be sent to the memory in two par ts within two consecutive rising clock edges. this minimizes the number of address signal connections betwe en the controller and the memory by reducing the address bus to a maximum of only 11 lines. sinc e the memory requires two clock cycles to read and wr ite the data, data bus efficiency is affected when operating in continuous burst mode with a burst length of 2 setting. bank addr esses are provided to the memory at the same time as the write and read commands together with the first address part, ax. the second address part, ay, is then issued to the memory on the next rising clock edge. aref commands only require the bank address. since aref commands do not need a second consecutive clock for address latching, they may be issued on consecutive clocks.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 17 a ddress mapping in multiplexed address mode data width burst length address ball a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 x9 2 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay a20 a1 a2 x a6 a7 a19 a11 a12 a16 a15 4 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 a19 a11 a12 a16 a15 8 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 x a11 a12 a16 a15 x18 2 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 a19 a11 a12 a16 a15 4 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 x a11 a12 a16 a15 8 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 x ay x a1 a2 x a6 a7 x a11 a12 a16 a15 n ote : x = dont care. on - die termination (odt) if the odt is enabled, the d s, qs and dm are terminated to v tt with a resist ance r tt . the command, address, qvld, and clock signals are not terminated. f igure 3.1 show s the equivalent circuit of a d receiver with odt. the odt function is d ynamically switched off when a q begins to drive after a read command is issued. similarly, o dt i s designed to switch on at the qs after the memory has issued the last piece of data. the d and dm pin s will always be terminated. odt dc parameters table description symbol min max units notes termination voltage v tt 0.95 x v ref 1.05 x v ref v 1, 2 on - die termination r tt 125 185 3 notes: 1. all voltages referenced to v ss (gnd). 2. v tt is expected to be set equal to v ref and must track variations in the dc level of v ref . 3. the r tt value is measured at 95c t c . r tt receiver d v tt switch figure 3.1 odt equivalent circuit
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 18 3.6 deselect /no operation ( desl/nop ) the deselect command is used to prevent unwanted operations fr om being performed in the memory device during wait or idle states. operations already registered to the memory prior to the assertion of the deselect command will not b e cancelled. 3.7 read o peration (read) the read command performs burst - oriented data read accesses in a bank of the memory device. the read command is initiated by registering the we# and ref# signals logic high while the cs# is in logic low state. in non - multiplexed address mode, both an address and a bank addres s must be provided to the memory during the assertion of the read command. in multiplexed mode, the bank address and the first part of the address, ax, must be supplied together with the read comma nd. the second part of the address, a y, must be latched to the memory on the subsequent rising edge of the ck clock. data being accessed will be available in the data bus a certain amount of clock cycles later depending on the read latency configuration se tting. data driven in the q signals are edge - aligned to the free - running output data clocks qkx and qkx#. a half clock cycle before the read data is available on the data bus, the data valid signal, qvld, will transition from logic low to high. the qvld s ignal is also edge - aligned to the data clock qkx and qkx#. if no other commands have been registered to the device when the burst re ad operation is finished, the q signals will go to high - z state. the qvld signal transition from logic high to logic low on the last bit of the read burst. please note that if ck/ck# violates the v id (dc) specification while a read burst is occurring, qvld will remain high until a dummy read command is registered. the qk clocks are free - running and will continue to cycle after the read burst is complete. back - to - back read commands are permitted which allows for a continuous flow of output data. a non-multiplexed mode ck # ck cs# we# ref# address ba* bank address don t care ax multiplexed mode ck # ck cs# we# ref# address ba* bank address ay read command
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 19 0 1 2 3 4 5 6 rd ba2 , a2 ba3 , a3 rd nop nop nop nop nop command address dont care undefined q2-1 q2-2 q3-1 q3-2 qvld q read latency = 4 ck ck # qkx qkx# t ckh t ckl t ck t ckqk t qkq t qkq t qkvld t qkvld t qkh t qkl basic read burst with qvld : bl=2 & rl=4 note s : 1. minimum rea d data valid window can be expressed as min(t qkh , t qkl ) C 2 x max (t qkqx ) . 2. t ckh and t ckl are recommended to have 50% / 50% duty. 3. t qkq0 is referenced to q0 C q 8 and t qkq1 is referenced to q9 C q17 in x18. 4. t qkq takes into account the skew between any qkx and an y q. 5. t ckqk is specified as ck rising edge to qk rising edge.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 20 ba1 , a1 ck # ck command address wr 0 1 2 3 4 5 6 7 rd rd nop nop nop nop ba2 , a2 ba3 , a3 nop nop 8 read latency = 4 write latency = 5 dk # dk d2-1 d2-2 d2-3 d2-4 d q1-1 q1-2 q1-3 q1-4 q q3-1 q3-2 q3-3 q3-4 qvld qk# qk don t care undefined read f ollowed by write: bl = 4, rl =4 & wl = 5, configuration 1 3.8 write operation (write) the write command performs burst - oriented data write accesses in a bank of the memory device. the write command is initiated by registering the ref# signal logic high while the cs# and we# signals are in logic low state. in non - multiplexed address mode, both an address and a bank addres s must be provided to the memory during the assertion of the write command. in multiplexed mode, the bank address and the first part of the address, ax, must be supplied together with the write command. the second pa rt of the address, a y, must be latched to the memory on the subsequent rising ed ge of the ck clock. input data to be written to the device can be registered several clock cycles later depending on the write latency configuration setting. the write latency is always one cycle longer than the programmed read latency. the dm signal can m ask the input data by setting this signal logic high. at least one nop command in between a read and write commands is required in order to avoid data bus contention. the setup and hold times for dm and data signals are t ds and t dh , which are referenced t o the dk clocks.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 21 a non-multiplexed mode ck # ck cs# we# ref# address ba* bank address don t care ax multiplexed mode ck # ck cs# we# ref# address ba* bank address ay write comma nd ck ck # dkx dkx # d1-0 d1-2 d1-3 d1-4 d write latency = 5 wr nop nop nop nop nop nop nop t ckdk t ds dm t dh masked data command 0 1 2 3 4 5 6 7 dont care undefined ba1 , a1 address basic write burst with dm timing : bl=4 & wl=5
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 22 0 1 2 3 4 5 6 7 8 9 wr wr rd ba1, a1 ba3 , a3 ba4 , a4 rd nop nop nop nop nop nop ck ck # command address dkx dkx# d1-1 d1-2 dont care undefined qvld d qkx qkx # write latency = 5 read latency = 4 q3-1 q3-2 q4-1 q4-2 q ba2, a2 d2-1 d2-2 write latency = 5 read latency = 4 write followed by read : bl = 2 , rl = 4 & wl = 5 , configuration 1 3.9 auto refresh command (aref) the auto refresh command performs a refresh cycle on one row of a specific bank of the memory . only bank addresses are required together with the control the pins. therefore, auto refresh commands can be issued on subsequent ck clock cycles on both multiplexed and non - multiplexed address mode. any command following an auto refresh command must meet a t rc timing delay or later. ck # ck cs# we# ref# address ba* bank address don t care auto refresh command
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 23 0 1 2 3 4 5 6 arefx bax bay arefy nop nop nop anycomx anycomy command b ank address dont care ck ck # q kx qkx# t ckh t ckl t ck bax bay t rc t rc aref example in t rc (t ck )=5 option: c onfig uration =5 command truth table operation code cs# we# ref# ax bax device deselect/no operation desl/nop h x x x x mode register set mrs l l l opcode x read read l h h a ba write write l l h a ba auto refresh aref l h l x ba n otes : 1. x = "don't care;" h = logic high; l = logic low; a = valid address; ba = valid bank address. 2. during mrs, only address inputs a0 - a17 are used. 3. address width changes with burst length. 4. all input states or sequences not shown are illegal or reserved. 5. all command and address in puts must meet setup and hold times around the rising edge of ck.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 24 3.11 on - die termination (odt) timing examples. read operation with odt : rl=4, bl=4 0 1 2 3 4 5 6 rd ba2 , a2 nop nop nop nop nop nop command address dont care undefined q2-0 qvld q read latency = 4 ck ck # qkx q kx# q odt on q odt nop q odt off q odt on 7 q2-1 q2-2 q2-3 t qkvld t qkvld read to write with odt: rl=4, bl=2 0 1 2 3 4 5 6 rd ba2 , a2 wr nop nop nop nop nop command address dont care q2-0 q2-1 qvld q read latency = 4 ck ck # qkx q kx# q odt on q odt nop q odt off q odt on 7 ba1 , a1 undefined t qkvld dkx dkx# write latency = 5 t qkvld d d1-0 d1-1
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 25 4 ieee 11 49.1 tap and boundary scan r ldram ? 2 memory devices have a serial boundary - scan test access port (tap) that allow the use of a limited set of jtag instructions to test the in terconnection between the memory i/os and printed circuit board traces or other co mponents. in conformance with ieee standard 1149.1, the memory contains a tap controller, instruction register, boundary scan register, bypass register, and id register. the tap operates in accordance with ieee standard 1149.1 - 2001 (jtag) with the exceptio n of the zq pin. to guarantee proper boundary - scan testing of the zq pin, mrs bit m8 needs to be set to 0 until the jtag testing of the pin is complete. note that on power up, the default state of mrs bit m8 is logic low. if the memory boundary scan regis ter is to be used upon power up and prior to the initialization of the device, the ck and ck# pins meet v id (dc) or cs# be held high from power up until testing. not doing so could result in inadvertent mrs commands to be loaded, and subsequently cause unex pected results from address pins that are dependent upon the state of the mode register. if these measures cannot be taken, the part must be initialized prior to boundary scan testing. if a full initialization is not practical or feasible prior to boundary scan testing, a single mrs command with desired settings may be issued instead. after the single mrs command is issued, the t mrsc parameter must be satisfied prior to boundary scan testing. 4.1 disabling the jtag feature the r ldram ? 2 memory can operate w ithout using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be left disconnected. they may alternately be connected to v dd through a pull - up resist or. tdo should be left disconnected. on power - up, the device will come up in a reset state, which will not interfere with device operation. 4.2 test access port signal list: test clock (tck) this signal uses v dd as a power supply. the test clock is used on ly with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) this signal uses v dd as a power supply. the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. test data - in (tdi) this signal uses v dd as a power supply. the tdi input is used to serially input test instructions and information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. tdi is connected to the most significant bit (msb) of any register. for more information r egarding instruction register loading, please see the tap controller state diagram. test data - out (tdo) this signal uses v ddq as a power supply. the tdo output ball is used to serially clock test instructions and data out from the registers. the tdo output driver is only active during the shift - ir and shift - dr t ap controller states. in all other states, the tdo pin is in a high - z state. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. for more information, please see the tap controller state diagr am.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 26 4.3 tap controller state and block diagram test logic reset select dr run test idle 0 1 select ir 1 capture dr 0 capture ir 0 shift dr exit1 dr 1 0 pause dr 0 exit2 dr update dr 1 1 shift ir exit1 ir 1 0 pause ir 0 exit2 ir update ir 1 1 0 1 0 0 1 0 1 0 0 1 1 1 0 0 0 1 1 note 1 bypass register (1 bit) identification register (32 bits) instruction register (8 bits) tap controller tdo tms tck tdi control signals note : 11 3 boundary scan registers in r ldram ? 2 memory
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 27 4.4 performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edg es of tck. reset may be performed while the sram is operating and does not affect its operation. at power - up, the tap is internally reset to ensure that tdo comes up in a high - z state. 4.5 tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry . only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the ris ing edge of tck and output on the tdo pin on the falling edge of tck. instruction register this register is loaded during the update - ir state of the tap controller. at power - up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is pla ced in a reset state as described in the previous section. when the tap controller is in the capture - ir state, the two lsbs are loaded with a binary 01 pattern to allow for fault isolation of the board - level serial test data path. bypass register the byp ass register is a single - bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the memory device with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and b idirectional balls on the device . several balls are also included in the scan register to reserved balls. the boundary scan register is loaded with the contents of the memory input and output ring when the tap controller is in the capture - dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift - dr state. each bit corresponds t o one of the balls on the device package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor - specific, 32 - bit code during the capture - dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the device and can be shifted out when the tap controller is in the shift - dr state. 4.6 scan register sizes register name bit size instruction register 8 bypass register 1 boundary scan register 113 identification (id) register 32
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 28 4.7 tap i nstruction set many instructions are possible with an eight - bit instruction register and all valid combinations are listed in the tap instruction code table. all other instruction codes that are not listed on this table are reserved and should not be used. instructions are loaded into the tap controller during the shift - ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted from the instruction register through the tdi and tdo pins. to execute an in struction once it is shifted in, the tap controller must be moved into the update - ir state. extest the extest instruction allows circuitry external to the component package to be tested. boundary - scan register cells at output balls are used to apply a test vector, while those at input balls capture test results. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary scan register using the preload instruction. thus, during the update - ir state of extest, the output driver is turned on, and the preload data is driven onto the output balls. idcode the idcode instruction causes a vendor - specific, 32 - bit code to be loaded into the identification register. it also places the identification register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift - dr state. the idcode instruction is loaded into the instruction register upon power - up or whenever the tap controller is given a test logic re set state. high - z the high - z instruction causes the b ypass register to be connected between th e tdi and tdo. this places all r ldram ? 2 memory outputs into a high - z state. clamp when the clamp instruction is loaded into the instruction register, the data dr iven by the output balls are determined from the values held in the boundary scan register. sample/preload when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture - dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequenc y up to 50 mhz, while the memory clock operates significantly faster. because there is a large difference between the clock frequencies, it is possible that during the capture - dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, b ut the re is no guarantee as to the value that will be captured. repeatable results may not be possible. to ensure that the boundary scan register will capture the corre ct value of a signal, the memory signal must be stabilized long enough to meet the tap control lers capture setup plus hold time (t cs plus t ch ). the memory clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/ preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible t o shift out the data by putting the tap into the shift - dr state. this places the boundary scan register betwe en the tdi and tdo balls. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift - dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 29 4.8 tap dc electrical characteristics and operating conditions ( +0c t c +95c; +1.7v v dd +1.9v, unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih v ref + 0.15 v ddq + 0.3 v 1, 2 input low (logic 0) voltage v il v ssq ? 0.3 v ref ? 0.15 v 1, 2 input leak age current 0v v in v dd i li ? 5 5 a output leakage current output disabled, 0v v in v ddq i lo ? 5 5 a output low voltage i olc =100 a v ol1 - 0.2 v 1 output low voltage i olt = 2ma v ol2 - 0.4 v 1 output high voltage |i ohc | =100 a v oh1 v ddq - 0.2 - v 1 output high voltage |i oht | = 2ma v oh2 v ddq - 0.4 - v 1 notes: 1. all voltages referenced to v ss (gnd). 2. overshoot = v ih (ac) v dd + 0.7v for t t ck /2; undershoot = v il (ac) C 0.5v for t t ck /2; during normal operation, v ddq must not exceed v dd . 4.9 tap ac electrical characteristics and operating conditions ( +0c t c +95c; +1.7v v dd +1.9v) description symbol min max units clock clock cycle time tthth 20 ns clock frequency ftf 50 mhz clock high time tthtl 10 ns clock low time ttlth 10 ns tdi/tdo times tck low to tdo unknown ttlox 0 ns tck low to tdo valid ttlov 10 ns tdi valid to tck high tdvth 5 ns tck high to tdi invalid tthdx 5 ns setup times tms setup tmvth 5 ns capture setup tcs 5 ns hold times tms hold ttmhx 5 ns capture hold tch 5 ns note : t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register.
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 30 4.10 tap timing 0 1 2 3 4 5 6 7 test mode clock (ck ) test mode s elect (tms) test data-in (tdi) t mvth t thmx t dvth t thdx test data-out (tdo) t tlox dont care undefined t thtl t tlth t thth t tlov 4.11 tap instruction codes instruction code description extest 0000 0000 captures input and output ring contents. places the boundary scan register between tdi and tdo. this operation does not affect device operations idcode 0010 0001 loads the id register with the vendor id code and places the register between tdi a nd tdo; this operation does not affect device operations sample/preload 0000 0101 captures i/o ring contents; places the boundary scan register between tdi and tdo clamp 0000 0111 selects the bypass register to be connected between tdi and tdo; data driv en by output balls are determined from values held in the boundary scan register high - z 0000 0011 selects the bypass register to be connected between tdi and tdo; all outputs are forced into high - z bypass 1111 1111 places the bypass register between tdi and tdo; this operation does not affect device operations note : all other remaining instruction codes not mentioned in the above table are reserved and should not be used. 4.12 identification (id) register definition instruction field all devices descri ption revision number (31:28) abcd ab = die revision cd = 00 for x9, 01 for x18, 10 for x36 device id (27:12) 00jkidef10100111 def = 000 for 288mb, 001 for 576mb i = 0 for common i/o, 1 for separate i/o jk = 01 for r ldram ? 2 memory vendor id co de (11:1) 000 1101 0101 allows unique identification of vendor id register presence indicator (0) 1 indicates the presence of an id register 4.13 tap input ac logic levels (+0c t c +95c; +1.7v v dd +1.9v, unless otherwise noted) description symb ol min max units input high (logic 1) voltage v ih v ref + 0.3 - v input low (logic 0) voltage v il - v ref - 0.3 v note: all voltages referenced to v ss (gnd).
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 31 4.14 boundary scan order signal name bump signal name bump signal name bump x9 x18 id x9 x18 id x9 x18 id 1 dk dk k1 39 d6 d11 r11 77 d1 d1 c11 2 dk# dk# k2 40 d6 d11 r11 78 d1 d1 c11 3 cs# cs# l2 41 d5 d10 p11 79 q1 q1 c10 4 ref# ref# l1 42 d5 d10 p11 80 q1 q1 c10 5 we# we# m1 43 q5 q10 p10 81 d0 d0 b11 6 a17 a17 m3 44 q5 q10 p10 82 d0 d0 b11 7 a16 a16 m2 45 d4 d9 n11 83 q0 q0 b10 8 a18 a18 n1 46 d4 d9 n11 84 q0 q0 b10 9 a15 a15 p1 47 q4 q9 n10 85 dnu q4 b3 10 dnu q14 n3 48 q4 q9 n10 86 dnu q4 b3 11 dnu q14 n3 49 dm dm p12 87 dnu d4 b2 12 dnu d14 n2 50 a19 a19 n12 88 dnu d4 b2 13 dnu d14 n2 51 a11 a11 m11 89 dnu q5 c3 14 dnu q15 p3 52 a12 a12 m10 90 dnu q5 c3 15 dnu q15 p3 53 a10 a10 m12 91 dnu d5 c2 16 dnu d15 p2 54 a13 a13 l12 92 dnu d5 c2 17 dnu d15 p2 55 a14 a14 l11 93 dnu q6 d3 18 dnu qk1 r2 56 ba1 ba1 k11 94 dnu q6 d3 19 dnu qk1# r3 57 ck# ck# k12 95 dnu d6 d2 20 dnu d16 t2 58 ck ck j12 96 dnu d6 d2 21 dnu d16 t2 59 ba0 ba0 j11 97 dnu d7 e2 22 dnu q16 t3 60 a4 a4 h11 98 dnu d7 e2 23 dnu q16 t3 61 a3 a3 h12 99 dnu q7 e3 24 dnu d17 u2 62 a0 a0 g12 100 dnu q7 e3 25 dnu d17 u2 63 a2 a2 g10 101 dnu d8 f2 26 dnu q17 u3 64 a1 a1 g11 102 dnu d8 f2 27 dnu q17 u3 65 a20 (a20) e12 103 dnu q8 f3 28 zq zq v2 66 qvld qvld f12 104 dnu q8 f3 29 q8 q13 u10 67 q3 q3 f10 105 (a21) (a21) e1 30 q8 q13 u10 68 q3 q3 f10 106 a5 a5 f1 31 d8 d13 u11 69 d3 d3 f11 107 a6 a6 g2 32 d8 d13 u11 70 d3 d3 f11 108 a7 a7 g3 33 q7 q12 t10 71 q2 q2 e10 109 a8 a8 g1 34 q7 q12 t10 72 q2 q2 e10 110 ba2 ba2 h1 35 d7 d12 t11 73 d2 d2 e11 111 a9 a9 h2 36 d7 d12 t11 74 d2 d2 e11 112 nf nf j2 37 q6 q11 r10 75 qk0 qk0 d11 113 nf nf j1 38 q6 q11 r10 76 qk0# qk0# d10 bit# bit# bit#
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 32 ordering information commercial range: t c = 0 to +95c; t a = 0c to +70c frequency speed order part no. organization package 533 mhz 1.875ns (trc=15ns) is49nls 9 32 00 - 18b 32 m x 9 144 f bga is49 nls 9 32 00 - 18bl 32 m x 9 144 f bga, lead - free is49 nls 18 160 - 18b 16 m x 18 144 f bga is49 nls 18 160 - 18bl 16 m x 18 144 f bga, lead - free 400 mhz 2.5ns (trc=15ns) is49 nls 9 32 00 - 25eb 32 m x 9 144 f bga is49 nls 9 32 00 - 25ebl 32 m x 9 144 f bga, lead - free is49 nls 18 160 - 25eb 16 m x 18 144 f bga is49 nls 18 160 - 25ebl 16 m x 18 144 f bga, lead - free 400 mhz 2.5ns (trc=20ns) is 49 nls 9 32 00 - 25b 32 m x 9 144 f bga is49 nls 9 32 00 - 25bl 32 m x 9 144 f bga, lead - free is49 nls 18 160 - 25b 16 m x 18 144 f bga is49 nls 18 160 - 25bl 16 m x 18 144 f bga, lead - free 300 mhz 3.3ns (trc=20ns) is49 nls 9 32 00 - 33b 32 m x 9 144 f bga is49 nls 9 32 00 - 33bl 32 m x 9 144 f bga, lead - free is49 nls 18 160 - 33b 16 m x 18 144 f bga is49 nls 18 160 - 33bl 16 m x 18 144 f bga, lead - free
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 33 ordering information industrial range: t c = ? 40c to 95c; t a = ? 40c to +85c frequency speed order part no. organization package 533 mhz 1.875ns (trc=15ns) is49 nls 9 32 00 - 18b i 32 m x 9 144 f bga is49 nls 9 32 00 - 18bl i 32 m x 9 144 f bga, lead - free is49 nls 18 160 - 18b i 16 m x 18 144 f bga is49 nls 18 160 - 18bl i 16 m x 18 144 f bga, lead - free 400 mhz 2.5ns (trc=15ns) is49 nls 9 32 00 - 25eb i 32 m x 9 144 f bga is49 nls 9 32 00 - 25ebl i 32 m x 9 144 f bga, lead - free is49 nls 18 160 - 25eb i 16 m x 18 144 f bga is49 nls 18 160 - 25ebl i 16 m x 18 144 f bga, lead - free 400 mhz 2.5ns (trc=20ns) is49 nls 9 32 00 - 25b i 32 m x 9 144 f bga is49 nls 9 32 00 - 25bl i 32 m x 9 144 f bga, lead - free is49 nls 18 160 - 25b i 16 m x 18 144 f bga is49 nls 18 160 - 25bl i 16 m x 18 144 f bga, lead - free 300 mhz 3.3ns (trc=20ns) is49 nls 9 32 00 - 33b i 32 m x 9 144 f bga is49 nls 9 32 00 - 33bl i 32 m x 9 144 f bga, lead - free is49 nls 18 160 - 33b i 16 m x 18 144 f bga is49 nls 18 160 - 33bl i 16 m x 18 144 f bga, lead - free
is49nls9 32 00,is49nls18 16 0 integrated silicon solution, inc. ? www.issi.com ? rev . 00 f, 09/ 2 5 /2012 34 ball grid array package code: b (144 - ball)

▲Up To Search▲

Price & Availability of IS49NLS18160

	To Download IS49NLS18160 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .